Field of the Invention
The present disclosure relates generally to a non-volatile memory, such as a flash memory device.
Description of Related Art
Among various types of a non-volatile memory such as flash memory devices, NAND-type flash memory devices are increasingly used as a high capacity data storage media. Each cell of a flash memory device is programmed to store information by trapping electrons in a floating gate. The programming operation is performed by driving a strong positive voltage on the control gate to force a current to flow from the channel through the floating gate to the control gate, a phenomenon known as the “Fowler Nordheim Tunneling” effect. A control gate terminal is connected to a word-line of the flash memory, and a voltage is provided to the control gate terminal through the word-line. Each memory cell can store a single bit which is called as single level memory cell (SLC), or alternatively, each cell can store multiple bits which is called as multiple level memory cell (MLC). In both SLC and MLC, information stored in each cell is defined by a corresponding threshold voltage of the memory cell.
FIG. 1 is a block diagram of an example of a flash memory device 100. According to the example of FIG. 1, the flash memory device 100 comprises a row decoder 10, a memory cell array 20, a page buffer block 30, and a data input/output (I/O) circuit 40. The memory cell array 20 is connected to the page buffet block. 30 through bit-lines BL and is connected to the row decoder 10 through word-lines WL and an additional conductive line. The additional conductive line may be, for example, a drain selection line or a source selection line for addressing a specific string. The memory cell array 20 includes a plurality of strings, each including a plurality of memory cells. Each memory cell, namely the floating gate of each memory transistor, stores data transferred from the page buffer block 30 under control of the row decoder 10, and transfers the stored data to the page buffer block 30 under control of the row decoder 10. Memory cells are arranged at the intersections of the plurality of bit-lines BL and the plurality of word-lines WL, respectively.
The page buffer block 30 is connected to the memory cell array 20 through the bit-lines BL. The page buffer block 30 is also connected to the data input/output circuit 40. The page buffer block 30 sets the bit-lines BL during program, read, and erase operations. The page buffer block 30 senses data stored in a memory cell of the memory cell array 20 during a read operation. The data input/output circuit 40 is connected to the page buffer block 30. The data input/output circuit 40 exchanges data DATA with an external device. The data input/output circuit 40 transfers write date to the page buffer block 30 for a writing operation. The data input/output circuit 40 may include components, such as a data buffer and a column pass gate (not shown), which are well known in the art.
The row decoder 10 is connected to the memory cell array 20. The row decoder 10 receives an external address ADDR for selecting a word line among the plurality of word lines WL1-WLm. The row decoder 10 is capable of driving the source selection line and the drain selection line of the string to which the addressed cells belong to. The row decoder 10 may apply various voltages, such as a program voltage, a pass voltage, a read voltage, and a ground voltage, to the word-lines WL according to the operation mode of the memory cell array 20.
FIG. 2 is a block diagram of the memory cell array 20 of the flash memory device 100 in FIG. 1.
The memory cell array 20 includes a plurality of blocks 50. Each block 50 includes a plurality of strings 60. Each string includes a plurality of memory cells in which data are stored. Memory cells are arranged at the intersections of the plurality of bit-lines BL0˜BLm and the plurality of word-lines WL0˜WLr+k−1, respectively. Strings can be selected or deselected by a drain selection line (e.g., DSL0, DSLj, DSLn), and by a source selection line (e.g., SSL0, SSLj, SSLn). Bit-lines BL0˜BLm of the memory cell array 20 are connected to the page buffer block 30 of FIG. 1. Word-lines WL, drain selection lines DSL and source selection lines SSL are connected to the row decoder 10 of FIG. 1.
FIG. 3 shows a detailed structure of respective strings and memory cells in the memory cell array 20 of FIG. 7.
FIG. 3 shows four strings 60 in the memory cell array 20. Each string 60 includes a plurality of memory cells 70 in which data is stored. In the example of FIG. 3, one string includes four memory cells, but the number of the memory cells included in one string may vary depending on design. The memory cells 70 are arranged at the intersections of the plurality of bit-lines BL0, BL1 and the plurality of word-lines WL0˜WL7, respectively. Strings can be selected or deselected by the drain selection line (e.g., DSL0, DSL1), and by the source selection line (e.g., SSL0, SSL1). Bit-lines BL0, BL1 of the memory cell array 20 are connected to the page buffer block 30 of FIG. 1. The word-lines WL0˜WL7, the drain selection lines DSL0, DSL1 and the source selection lines SSL0, SSL1 are connected to the row decoder 10 of FIG. 2.
The drain selection line DSL0 or DSL1 is connected to the gate of the drain select transistor DST of each string. The source selection line SSL0 or SSL1 is connected to the gate of the source select transistor SST of each string. To make a specific string be driven by the bit-line, a high voltage can be applied to the gate of the SST and the DST to switch them on. Thanks to the drain select transistor DST, the source select transistor SST, the source selection line SSL, and the drain selection line DSL, specific strings belonging to the same row can be specifically chosen to carry out one of operations such as program, erase, and read operations. The other strings, which are not selected for the operation, are decoupled from the bit-lines by applying a low voltage to the gates of the respective DST and SST of those strings.
FIG. 4A schematically is a block diagram of a page buffer block 30 and a data input/output (I/O) circuit 40 in FIG. 1. FIG. 4B is a detailed circuit diagram of a page buffer 400 of FIG. 4A.
The page buffer block 30 includes a plurality of page buffers PB0 to PBr including page buffers 400, 401 and 402. Each of the page buffers 400, 401, 402 is connected to the corresponding bit-lines penetrating though the memory cell array 20. Each of the page buffers 400, 401, 402 sets the corresponding bit-line BL during program, read, and erase operations, and senses the data stored in each memory cell of the memory cell array 20 during the read operation. The data input/output (I/O) circuit 40 is connected to the page buffer block 30.
The page buffer 400 of FIG. 4B comprises a first NMOS transistor N1 410, a PMOS transistor P1 420, a second NMOS transistor N2 430, and a latch 440 including a first inverter I1 and a second inverter I2. Any circuit elements unnecessary to explain the operation are omitted from the drawing.
The PBSENSE voltage is applied to the gate of the first NMOS transistor N1 410. The PMOS transistor P1 420 acts as a charge pump to provide a high voltage to the drain of the first NMOS transistor N1 410 when charging of the bit-line BL0 is required. The second NMOS transistor N2 430 is used for switching on and off the latch 440 between the pre-charging stage and the bit-tines sensing stage.
One page buffer may be connected to a plurality of bit-lines, for example, two bit lines including an even bit-line and an odd bit-line (not shown). In this case, two switching transistors may be arranged between the first NMOS transistor N1 and the two bit-lines. In other words, an odd bit-line switching transistor may be arranged between the first NMOS transistor N1 and the odd bit-line, and an even bit-line switching transistor may be arranged between the first NMOS transistor N1 and the even bit-line. Such configuration is known, and for simplicity of explanation, the odd bit-line switching transistor and the even bit-line switching transistor are not shown in the figures.
As the density of memory cells constantly increases in order to store more data in a given area, the distance or pitch between the bit lines BLs is drastically reduced, and the width of the bit lines BLs becomes smaller and smaller, therefore causing higher resistances of the bit-lines BLs. These high resistance values are not negligible for the read operation of a flash memory, because they introduce different biasing conditions for the operation of the memory device. Particularly, when a multiple level memory cell (MLC) scheme is used, requiring more sophisticated control, an incorrect bias can result in increased reading errors. Moreover, as the flash memory becomes older, the threshold voltage of each cell can deviate slightly from the desired value, which may also causes reading errors.
Therefore, a novel method for a more precise control of a read operation of a flash memory is needed.